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python matlab dsp systemverilog uvm📋 Description
- Responsible for digital ASIC verification at block and system level
- Write and review test plans, develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
- Responsible for test plan execution, running regressions, code and functional coverage closure
- Automate test case generation by using Python and MATLAB programs
- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
🎯 Requirements
- Bachelor’s degree in electrical engineering, computer science or computer engineering
- 2+ years of experience with design verification and test bench development
- Advanced degree in electrical engineering or computer engineering
- Experience with verification methodologies such as UVM
- Strong object-oriented programming knowledge
- Experience with scripting languages, e.g. Python for automation
🎁 Benefits
- Pay range: Level I $130k-$155k; Level II $150k-$180k
- Equity and long-term incentives; stock options; ESPP
- Medical, vision, dental coverage; 401(k); disability and life insurance
- Paid parental leave; vacation and holidays; sick leave
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