Understand chip and subsystem architecture.
Develop, maintain, and extend UVM-based verification environments.
Write test plans, test cases, and sequences for block- and chip-level verification.
Debug design issues based on architectural specifications.
Work with design and architecture teams to meet quality and schedule goals.

🎯 Requirements

BSEE/MSEE or equivalent in EE, CS, or related field.
Proficient in Verilog/SystemVerilog and UVM.
Comfortable working in Linux and with industry-standard EDA tools.
Solid grasp of verification methodologies and design processes.
Excellent teamwork and communication skills.
Experience with functional and code coverage analysis.

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