Related skills
cadence asic power integrity physical design timing closure📋 Description
- Implement digital blocks in advanced nodes from synthesis to physical verification.
- Understand timing constraints, derates and margins; review STA reports and fix timing.
- Build and customize power grid; ensure power integrity goals are met.
- Understand clock details and customize clock implementation for functional and test clocks.
- Debug and clean up DRC/LVS.
- Functional and timing ECO implementation.
🎯 Requirements
- Bachelor’s in Electrical Engineering or Computer Engineering
- 8+ years of industry experience as a Physical Design Engineer
- Must have completed blocks or top-level physical design for large ASICs or mixed-signal chips that taped out
- Thorough knowledge of timing closure, LVS/DRC closure
- Experience in TCL and Python (or other scripting languages)
- Strong teamwork skills with the ability to collaborate across multiple functional teams
🎁 Benefits
- Comprehensive Health Care Plan (Medical, Dental & Vision)
- Retirement Savings Matching Program
- Life Insurance (Basic, Voluntary & AD&D)
- Generous Time Off (Vacation, Sick & Public Holidays)
- Paid Family Leave
- Flexible, hybrid workplace model
Meet JobCopilot: Your Personal AI Job Hunter
Automatically Apply to Engineering Jobs. Just set your
preferences and Job Copilot will do the rest — finding, filtering, and applying while you focus on what matters.
Help us maintain the quality of jobs posted on Empllo!
Is this position not a remote job?
Let us know!