Sr. Staff Physical Design Timing Engineer (STA)

📋 Description

• Drive the STA sign-off for our silicon photonics chips at various nodes.
• Analyze fab guidelines and incorporate sign-off corners and derates.
• Collaborate with architecture, RTL, and DFT teams to define timing constraints.
• Analyze power, performance, and area tradeoffs for chip implementation.
• Run full-chip STA and project timing summary across scenarios.
• Leverage Tempus/PrimeTime to automate timing ECOs and closures.

🎯 Requirements

• Bachelor's degree in Electrical Engineering or Computer Engineering.
• 12 years in Physical Design with 5+ years in ASIC STA timing with Cadence or Synopsys.
• Drive timing closure, manage on-chip variation derates, and clock-tree strategies.
• Scripting: TCL, Python, PERL, or Shell.
• Strong problem solving with attention to detail.
• Strong team player with clear communication.

🎁 Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability