Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

📋 Description

• Perform partition synthesis and physical implementation (synthesis, floorplanning, P&R, timing, signoff)
• Develop/Improve physical design methods and automation scripts
• Collaborate with ASIC design team on feasibility studies, timing/power/area targets, RTL/design tradeoffs
• Resolve design/timing/congestion issues and drive execution
• Run and fix signoff issues in STA, noise, and verification

🎯 Requirements

• Bachelor's degree in electrical, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience
• ASIC/SOC RTL2GDSII design and signoff flows
• Proficiency with industry EDA tools and workflows
• Knowledge of deep sub-micron FinFET/CMOS physics
• Scripting: Python, Perl, TCL, Bash

🎁 Benefits

• Equity incentives and stock options
• Medical, vision, dental coverage
• 401(k) retirement plan
• Disability and life insurance
• Paid parental leave
• 3 weeks vacation and 10+ holidays; sick leave