Sr. RTL Design Engineer (Silicon Engineering)

Added
2 days ago
Type
Full time
Salary
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Related skills

python asic soc verilog systemverilog

πŸ“‹ Description

  • Evaluate architectural trade-offs based on features, performance, and limits
  • Define micro-architecture and RTL in Verilog/SystemVerilog; integrate and verify
  • Work with verification team to ensure all aspects are covered and verified
  • Provide timing constraints for IPs and support synthesis, timing closure, formal checks
  • Participate in silicon bring-up and validation

🎯 Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • 5+ years of RTL implementation
  • Clock domain crossings and power optimization
  • ASIC/SoC system integration experience
  • Experience with Python scripting
  • Ability to work extended hours or weekends as needed for mission critical deadlines

🎁 Benefits

  • Stock options and long-term incentives
  • Comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • Paid parental leave
  • Paid vacation and holidays
  • Employee stock purchase plan (ESPP) and stock purchase opportunities
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