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python asic soc verilog systemverilog📋 Description
- Evaluate architectural trade-offs based on features and system limits.
- Define micro-architecture; implement RTL in Verilog/SystemVerilog; integrate and deliver verified design.
- Collaborate with verification to ensure complete design verification.
- Provide timing constraints for IPs and support synthesis and timing closure.
- Participate in silicon bring-up and validation.
🎯 Requirements
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- 5+ years RTL implementation experience
- ASIC/SoC system integration experience
- Experience with embedded CPU subsystems
- Experience with standard bus protocols AXI, AHB, etc.
- Experience with high speed and low power design techniques
🎁 Benefits
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long term disability insurance
- Life insurance and paid parental leave
- Paid vacation and holidays; 3 weeks vacation + 10+ holidays per year
- Employee stock purchase plan and stock options
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