Sr. RTL Design Engineer (Silicon Engineering)

📋 Description

• Evaluate architectural trade-offs based on features and system limits
• Define micro-architecture; implement RTL in Verilog/SystemVerilog
• Integrate RTL into top level; deliver the fully verified, synthesis/timing-clean design
• Work closely with verification to cover all design aspects
• Provide timing constraints and support the physical implementation team

🎯 Requirements

• Bachelor’s degree in electrical/computer engineering or CS
• 5+ years RTL implementation experience
• ASIC/SoC system integration experience
• Experience with AXI/AHB and bus protocols
• Scripting skills (Python)
• EDA tools like HDL simulators and lint tools