Related skills
python asic soc verilog systemverilog📋 Description
- Evaluate architectural trade-offs based on features and performance
- Define micro-architecture; implement RTL in Verilog/SystemVerilog; deliver verified design
- Collaborate with verification to ensure full design coverage
- Provide timing constraints for IPs; support synthesis and timing closure
- Participate in silicon bring-up and validation
🎯 Requirements
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- 5+ years RTL implementation experience
- ASIC/SoC system integration experience
- Experience with multicore CPU subsystem design
- Experience with standard bus protocols (AXI, AHB, etc.)
- Scripting skills (Python, TCL)
🎁 Benefits
- Stock options and long-term incentives
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Disability and life insurance
- Paid parental leave
- Paid vacation and holidays
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