Related skills
python asic soc verilog systemverilog📋 Description
- Evaluate architectural trade-offs on features and system limits
- Define micro-architecture; implement RTL in Verilog/SystemVerilog; deliver verified design
- Collaborate with verification to ensure full design coverage
- Provide timing constraints; support synthesis, timing closure, formality checks
- Participate in silicon bring-up and validation
🎯 Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 5+ years of RTL implementation
- ASIC/SoC system integration experience
- Experience with embedded CPU subsystems
- Experience with standard bus protocols (e.g. AXI, AHB)
- Scripting skills (Python)
🎁 Benefits
- Stock options and long-term incentives
- 401(k) retirement plan
- Medical, vision, and dental coverage
- Life and disability insurance
- Paid parental leave
- Paid vacation and holidays
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