Sr. RFIC Layout Designer (RFIC Engineering)

📋 Description

• Define chip floor plan with power/ground and pad locations.
• Estimate layout schedule and flag complex areas early.
• Layout RF/analog blocks with matching and low parasitics.
• Run DRC/ER/LVS and resolve errors.
• Integrate top-level layout with ESD, pads, density fill, and tape-out.
• Collaborate with EDA vendors to trial tools.
• Create guides/demos to share layout techniques.

🎯 Requirements

• Bachelor's in Electrical/Computer Eng +5+ yrs IC layout; or 8+ yrs exp w/o degree.
• Strong analog RF layout experience.
• Experience with advanced nodes: 22nm/16nm/7nm/5nm or below.
• Experience with RF blocks: LNA, VCO, mixers.
• Programming: Python, Perl or shell; Linux proficiency.
• Experience with DRC/ER/LVS and GDS sharing; revision control.

🎁 Benefits

• Equity and long-term incentives including stock options.
• Medical, vision, dental coverage.
• 401(k) retirement plan.
• Paid parental leave.
• 3 weeks paid vacation and 10+ paid holidays.
• Sick leave for exempt employees.