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python systemverilog uvm rtl vcs📋 Description
- Define HW architecture and evaluate design trade-offs for performance, area, and power.
- Lead RTL development, integration, and verification through the design cycle.
- Partner with firmware and verification teams to ensure top-quality silicon delivery.
- Mentor and review junior engineers' work; promote best practices.
- Provide design-in and bring-up support for customer-facing projects.
🎯 Requirements
- Strong command of SystemVerilog for RTL design and digital architecture.
- Experience using simulation tools such as Questa, Incisive, or VCS.
- Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
- Proven experience in ASIC or FPGA design, synthesis, and timing closure.
- Familiarity with UVM-based verification environments.
- Understanding of AMBA AXI or CHI protocols.
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