Own and execute full-chip DRC/LVS/ESD/PERC and antenna signoff using Calibre, ICV, Pegasus
Develop, maintain, and optimize physical verification flows for advanced node SoCs
Interpret and implement foundry DRM — translate rule updates into verified flow changes
Debug DRC/LVS violations across hierarchical full-chip designs
Perform ESD verification and validate protection strategies (CDM/HBM)
Drive tapeout readiness by coordinating signoff across block/top-level and Hard IP teams

🎯 Requirements

Bachelor’s degree in electrical engineering, computer engineering or computer science
5+ years of ASIC and/or physical design flow development experience in industry

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