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esd perc lvs drc calibre📋 Description
- Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using Calibre, ICV, Pegasus
- Develop, maintain, and optimize physical verification flows for advanced node SoCs
- Interpret and implement foundry DRM — translate rule updates into verified flow changes
- Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
- Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
- Engage directly with foundry teams to resolve DRM ambiguities and waiver requests
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