Implement/optimize DFT architectures (scan insertion, memory BIST, logic BIST) with Tessent.
Integration and verification of DFT IPs and fabrics within Subsystems
Set up ATPG; generate patterns for stuck-at/transition/path tests; focus on compression/diagnosis.
Run and debug non-timing and SDF annotated gate-level simulations
Create/validate DFT patterns for post-silicon bringup; assist ATE debugging.
Develop test scripts, automate processes, and analyze data using Perl, Python, Tcl, or C++

🎯 Requirements

Bachelor's degree in electrical engineering, computer engineering, or physics
5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

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