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python matlab dsp systemverilog uvm📋 Description
- Digital ASIC verification at block and system level
- Lead and execute verification test plans; develop harnesses and sequences
- Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for DSP blocks
- Execute test plans, run regressions, and drive code and functional coverage closure
- Automate test case generation with Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up and post-silicon validation
🎯 Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 5+ years of design verification and test bench development
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong object-oriented programming knowledge
- Strong problem-solving and coding skills
- Experience with scripting languages, e.g., Python for automation
🎁 Benefits
- Competitive compensation and long-term incentives
- Equity options and potential bonuses
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan with company match
- Paid vacation and holidays
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