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python matlab dsp systemverilog uvm📋 Description
- Responsible for digital ASIC verification at block and system level
- Lead and execute verification test plans; develop test harnesses and milestones
- Develop SystemVerilog testbenches (UVM and non-UVM) for DSP blocks
- Execute test plans, run regressions, and close code/functional coverage
- Automate test case generation using Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up and post-silicon validation
🎯 Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 5+ years of design verification and test bench development
- Experience with UVM/OVM/VMM and constrained random verification
- Strong object-oriented programming knowledge and coding skills
- Experience with Python and MATLAB for automation
- RTL design, chip bring-up, and post-silicon validation experience
🎁 Benefits
- Stock options and long-term incentives, including Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage; 401(k) retirement plan
- Disability and life insurance
- Paid parental leave; 3 weeks vacation and 10+ paid holidays
- Potential discretionary bonuses and equity opportunities
- Employee discounts and other perks
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