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python matlab dsp systemverilog uvm📋 Description
- Responsible for digital ASIC verification at block and system level
- Lead and execute verification test plan, develop test harnesses and sequences
- Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for testing designs
- Test plan execution, running regressions, coverage closure
- Automate test case generation using Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up and post-silicon validation
🎯 Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 5+ years of experience with design verification and test bench development
- Advanced degree in electrical engineering or computer engineering
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong object-oriented programming knowledge
- Experience with scripting languages, e.g. Python for automation
🎁 Benefits
- Stock options and long-term incentives
- Comprehensive health, dental, and vision coverage
- 401(k) retirement plan with company match
- Paid parental leave and paid time off
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