Sr. ASIC Design Verification Engineer (Silicon Engineering)

Added
2 days ago
Type
Full time
Salary
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Related skills

python test plans verification uvm rtl

πŸ“‹ Description

  • Responsible for digital ASIC verification at block and system level
  • Write and review test plans, develop test harnesses and sequences
  • Execute test plans, run regressions, and close code/functional coverage
  • Contribute to pre-silicon verification, chip bring-up and post-silicon validation
  • Hands-on self-starter who can verify complex digital designs

🎯 Requirements

  • Bachelor's degree in electrical or computer engineering
  • 5+ years design verification and test bench development
  • Advanced degree in electrical or computer engineering
  • Experience with UVM/OVM/VMM verification methodologies
  • Strong object-oriented programming knowledge
  • Experience in constrained random verification and Python automation

🎁 Benefits

  • Stock options and long-term incentives
  • Medical, vision, dental coverage
  • 401(k) retirement plan with company match
  • Paid parental leave and vacation
  • Paid holidays and sick leave
  • Employee discounts and perks
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