Sr. ASIC Design Engineer (Starshield)

📋 Description

• Design digital ASICs and/or FPGAs for Starshield projects.
• Partition functions between hardware and software domains.
• Define micro-architecture; RTL in Verilog/SystemVerilog.
• Collaborate with verification to ensure design coverage.
• Provide timing constraints; support synthesis and timing closure.
• Participate in silicon bring-up and lab measurements.

🎯 Requirements

• Bachelor's degree in electrical/computer engineering or CS.
• 5+ years RTL/FPGA/ASIC development.
• Clock domain crossings and power optimization experience.
• Experience with complex ASICs.
• Multicore CPU subsystem design experience.
• Familiar with AXI/AHB and related buses.
• Scripting: Python or TCL; HDL tools (VCS/Questa).

🎁 Benefits

• Stock options and equity incentives.
• 401(k) retirement plan with company match.
• Medical, vision, and dental coverage.
• Disability and life insurance.
• Paid parental leave; vacation and holidays.
• Employee stock purchase plan.