Related skills
fpga asic verilog systemverilog axi📋 Description
- Design digital ASICs and/or FPGAs for Starshield.
- Derive specs; trade-offs; coordinate HW/SW partitioning with modem/DSP and RFIC teams.
- Define micro-architecture; RTL in Verilog/SystemVerilog; integrate and verify.
- Collaborate with verification team to ensure full design verification.
- Provide timing constraints; support synthesis, timing closure, and formal checks.
- Participate in silicon bring-up and test-lab equipment development.
🎯 Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science.
- 5+ years of RTL implementation and/or FPGA/ASIC development.
🎁 Benefits
- Stock options and long-term incentives.
- Medical, vision, and dental coverage; 401(k).
- Paid parental leave and generous vacation/holidays.
- Disability and life insurance; employee discounts.
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