Sr. ASIC Design Engineer (Silicon Engineering)

📋 Description

• Evaluate architectural trade-offs based on features, perf and limits
• Define micro-architecture and implement RTL in Verilog/SystemVerilog
• Integrate RTL into top level and deliver fully verified, timing-clean design
• Work with verification to ensure full coverage and validation
• Provide timing constraints for IPs and support synthesis
• Participate in silicon bring-up and validation

🎯 Requirements

• Bachelor’s degree in electrical, computer engineering, or CS
• 5+ years of RTL implementation experience
• ASIC/SoC system integration experience
• Experience with embedded CPU subsystems
• Experience with bus protocols (AXI, AHB, etc.)
• Python scripting and HDL tools experience

🎁 Benefits

• Medical, vision, and dental coverage
• 401(k) retirement plan
• Disability and life insurance
• Paid parental leave
• Paid vacation and holidays
• Stock options and ESPP