Sr. ASIC Design Engineer (Silicon Engineering)

📋 Description

• Evaluate architectural trade-offs based on features and limits
• Define micro-architecture; implement RTL in Verilog/SystemVerilog
• Integrate RTL into top level; deliver verified, synthesis-ready design
• Collaborate with verification team to ensure coverage
• Provide timing constraints for IPs; support synthesis and timing closure
• Participate in silicon bring-up and validation

🎯 Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 5+ years RTL implementation
• Clock-domain crossing and power optimization
• ASIC/SoC system integration experience
• Embedded CPU subsystems experience
• AXI/AHB and bus protocols

🎁 Benefits

• Medical, vision, and dental coverage
• 401(k) retirement plan
• Short/long-term disability and life insurance
• Paid parental leave
• Paid vacation and holidays
• Employee stock purchase plan and stock options