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python asic soc uvm rtl📋 Description
- Responsible for digital ASIC verification at block and system level
- Write and review test plans; develop test harnesses and sequences
- Execute test plans; run regressions; ensure code and functional coverage closure
- Contribute to pre-silicon verification, chip bring-up, and post-silicon validation
- Collaborate with cross-disciplinary teams to verify complex digital designs
🎯 Requirements
- Bachelor's degree in electrical engineering or computer engineering
- 5+ years of design verification and test bench development
- Advanced degree in electrical engineering or computer engineering
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong object-oriented programming knowledge
- RTL design, chip bring-up, and post-silicon validation experience
🎁 Benefits
- Pay range: $170k-$230k/year
- Stock options and long-term incentives
- Medical, vision, and dental coverage
- 401(k) retirement plan and disability insurance
- Paid parental leave; 3 weeks vacation; 10+ holidays
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