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python matlab asic systemverilog uvm📋 Description
- Responsible for digital ASIC verification at block and system level
- Write and review test plans; develop test harnesses and sequences
- Develop SystemVerilog testbenches (UVM and non-UVM) for designs
- Execute test plans, run regressions, and close code and functional coverage
- Automate test case generation using Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up and post-silicon validation
🎯 Requirements
- Bachelor's degree in electrical engineering, computer science or computer engineering
- 1+ years of experience with design verification and test bench development
- Advanced degree in electrical or computer engineering
- Experience with verification methodologies such as UVM
- Strong object-oriented programming knowledge
🎁 Benefits
- Pay range: Level I $122,500-$145,000; Level II $140,000-$170,000 per year
- Stock options and long-term incentives; 401(k), medical, dental
- 3 weeks vacation, 10+ holidays, 5 sick days for exempt
- EOE; accommodations available on request
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