Digital ASIC verification at block and system level
Write and review test plans; develop harnesses and sequences
Develop SystemVerilog testbench infra (UVM and non-UVM)
Execute test plans, run regressions, and close coverage
Automate test case generation using Python and MATLAB
Contribute to pre-silicon verification, chip bring-up and post-silicon validation

🎯 Requirements

Bachelor’s degree in electrical engineering, computer science or computer engineering
2+ years of experience with design verification and test bench development

🎁 Benefits

Stock options and long-term incentives
Employee Stock Purchase Plan
Medical, Vision, and Dental coverage
401(k) retirement plan
Short/long-term disability and life insurance
Paid parental leave and 3+ weeks vacation

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