Analyze architectural specs and define verification requirements.
Develop and maintain UVM-based verification environments.
Create detailed test plans and develop test cases.
Debug functional issues and perform root-cause analysis.
Collaborate with design and architecture teams to align milestones and quality metrics.

🎯 Requirements

Bachelor’s or Master’s degree in EE, CS, or a related field.
7–10+ years of experience in verification or similar roles.
Strong SystemVerilog and UVM expertise.
Familiarity with Linux and standard EDA tools.
Thorough understanding of the pre-silicon design and verification flow.
Excellent communication, documentation, and teamwork skills.

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