Own end-to-end chip-level STA and sign-off across checks, modes, corners, V, and T.
Develop, maintain, and validate sign-off SDC constraints for clocks, resets, DFT.
Drive timing closure at block/full-chip levels via critical-path analysis, ECOs, and PD.
Perform MMMC timing analysis including CDC timing and OCV/AOCV/POCV methodologies.
Lead signal integrity and crosstalk analysis; identify and mitigate timing issues.
Conduct pre-/post-silicon timing correlation and sign-off readiness reviews and tape-out closure.

🎯 Requirements

Bachelor’s degree in Electrical or Computer Engineering; Master’s preferred.
10+ years hands-on chip-level STA ownership and timing sign-off across multiple tape-outs at 22nm or below.
Deep expertise with Cadence Tempus.
MMMC timing analysis including OCV/AOCV/POCV, SI, and crosstalk.
Hierarchical SDC constraints for large SoCs with multiple clock/power domains.
Python and Tcl scripting for automation.

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