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python fpga asic vhdl verilog📋 Description
- Design ASICs/FPGA for Starlink; implement IP for complex SoCs using Verilog/SystemVerilog
- Participate in full ASIC/FPGA design lifecycle from concept to validation with backend teams
- Engage in high-level architectural design for FPGA and ASICs
- Collaborate with cross-functional teams to develop Starlink tech for user terminals and satellites
🎯 Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
- 1+ years of RTL Design experience with SystemVerilog, Verilog or VHDL
- ASIC/FPGA system integration experience
- Proficiency in Python for scripting
- Experience with AXI/AHB/APB protocols
- Ability to work extended hours or weekends as needed for mission critical deadlines
🎁 Benefits
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short- and long-term disability and life insurance
- Paid parental leave
- Paid vacation (3 weeks) and 10+ holidays per year
- Sick leave for exempt employees (5 days/year)
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