Related skills
architecture simulation verilog synthesis systemverilog📋 Description
- Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
- Contribute to architectural studies including performance modeling and feasibility analysis
- Collaborate with software, simulator, and compiler teams for hw/sw co-design and workload fit
- Partner with DV and PD to ensure correctness, timing, area/power targets, and clean integration
- Build and review performance and functional models to validate design intent
- Participate in design reviews, documentation, and bring-up across the silicon lifecycle
🎯 Requirements
- Graduate-level work in computer architecture and AI/ML HW/SW co-design (workload analysis)
- Expertise writing RTL in Verilog/SystemVerilog with blocks delivered to tape-out
- Experience developing hardware design models or architectural simulators for AI/ML or HPC systems
- Familiarity with design tools (lint, CDC/RDC, synthesis, STA) and methodologies
- Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams
- Strong problem-solving across abstraction layers from algorithms to circuits
- Passion for building massive-scale hardware systems
🎁 Benefits
- Relocation assistance
- Hybrid work model (3 days in office per week)
🚚 Relocation support
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