Lead verification planning and execution at block/full-chip level.
Partner with architects and designers to align verification goals with design intent.
Build, enhance, and maintain UVM-based verification environments.
Achieve and track coverage metrics to ensure complete functional validation.
Collaborate with lab teams for silicon bring-up and debug.
Drive verification methodology improvements and mentor team members.

🎯 Requirements

MSEE with 10+ years or PhD with 7+ years in verification.
Advanced knowledge of SystemVerilog and UVM.
Proficiency with VCS, Xcelium, and IMC.
Strong scripting and automation skills (Python, Perl).
Excellent communication and cross-functional leadership.

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