Lead DFT architecture implementation and optimization (scan insertion, BIST) with Siemens Tessent.
Own ATPG tools and patterns for stuck-at, transition, and path-delay faults; post-silicon support.
Assess RTL and physical design readiness for scan insertion using DRC tools.
Integrate and verify DFT fabrics and IP in Subsystems.
Run and debug non-timing and SDF-annotated gate-level simulations.
Develop test scripts and automation in Perl, Python, Tcl, or C++.

🎯 Requirements

B.S. in electrical/computer engineering or computer science.
10+ years of ASIC experience.
10+ years in scan insertion and DFT setup, integration, validation.

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