Lead DFT architecture: scan insertion, compression, memory BIST; Tessent.
Own ATPG: patterns for stuck-at, transitions, path delays; post-silicon validation.
Evaluate scan-readiness via RTL and physical design DRC checks.
Integrate DFT fabrics and IP within Subsystems.
Run and debug non-timing and SDF-annotated gate-level sims.
Develop test scripts and automate with Perl, Python, Tcl, or C++.

🎯 Requirements

Bachelor’s degree in EE, CE, or CS.
10+ years of ASICs experience.
10+ years in scan insertion and DFT setup/integration.

🎁 Benefits

Stock options and long-term incentives.
Employee Stock Purchase Plan.
Medical, vision, and dental coverage.
401(k) retirement plan and disability insurance.
Paid vacation, holidays, and sick leave.

Apply on employer's website

This employer gathers applications via their own applicant tracking system.

You will be redirected to an external application form.

Share job

Meet JobCopilot: Your Personal AI Job Hunter

Automatically Apply to Engineering Jobs. Just set your preferences and Job Copilot will do the rest — finding, filtering, and applying while you focus on what matters.

Activate JobCopilot