Lead DFT architecture implementation using Siemens Tessent for RTL/gate nets
Own ATPG tools/patterns for stuck-at/transition/path delay; post-silicon testing
Evaluate design readiness for scan insertion using RTL and physical design DRC tools
Integrate/verify DFT fabrics and IP within subsystems
Run and debug non-timing and SDF-annotated gate-level simulations
Develop test scripts and automate processes; analyze data with Perl, Python, Tcl, or C++

🎯 Requirements

Bachelor’s degree in electrical/computer engineering or CS
10+ years of experience with ASICs
10+ years in scan insertion and DFT setup/integration/validation
Willing to work extended hours and weekends

🎁 Benefits

Stock options and long-term incentives
Medical, vision, and dental coverage
401(k) retirement plan
Paid vacation and holidays; sick leave

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