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python fpga asic uvm rtl๐ Description
- Responsible for digital ASIC and/or FPGA verification at block and system level
- Lead and execute verification test plan, development, and milestones from beginning to end
- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
- Hands-on self-starter who can verify complex digital designs
๐ฏ Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 10+ years of experience with design verification and test bench development
- ITAR: U.S. citizen/national or eligible for export authorization
- Advanced degree in electrical or computer engineering
- Experience with verification methodologies such as UVM/OVM/VMM
- Experience in constrained random verification
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