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python fpga asic uvm rtl📋 Description
- Responsible for digital ASIC/FPGA verification at block and system level
- Lead verification test plan, development, and milestones end-to-end
- Contribute to pre-silicon verification, chip bring-up, post-silicon validation
- Hands-on self-starter who can fully verify a complex digital design
🎯 Requirements
- Bachelor's degree in electrical/computer engineering or computer science
- 10+ years in design verification and test bench development
- Experience with verification methodologies such as UVM/OVM/VMM
- Advanced degree in electrical/computer engineering (preferred)
- Strong object-oriented programming knowledge and Python scripting
- RTL design, chip bring-up, and post-silicon validation experience
🎁 Benefits
- Long-term incentives such as stock options
- Employee Stock Purchase Plan
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Disability and life insurance
- Paid vacation, holidays, and sick leave
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