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1 day ago
Type
Full time
Salary
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python fpga asic uvm rtlπ Description
- Verify digital ASIC/FPGA at block and system level
- Lead and execute verification test plans and milestones
- Contribute to pre-silicon, chip bring-up, and post-silicon validation
- Hands-on self-starter able to fully verify complex digital designs
π― Requirements
- Bachelorβs degree in electrical engineering, computer engineering, or computer science
- 10+ years of design verification and test bench development experience
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong object-oriented programming knowledge
- RTL design, chip bring-up, and post-silicon validation experience
- Experience with scripting languages, e.g., Python for automation
π Benefits
- Medical, vision, dental coverage
- 401(k) retirement plan
- Short/long-term disability and life insurance
- Paid parental leave
- 3 weeks paid vacation and 10+ holidays per year
- Stock options and long-term incentives
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