Related skills
python matlab dsp systemverilog uvm📋 Description
- Digital ASIC verification at block and system level.
- Lead and execute verification plans; develop harnesses.
- Develop SystemVerilog testbenches (UVM and non-UVM) incl. DSP blocks.
- Execute test plans, run regressions, and close coverage.
- Automate test case generation using Python and MATLAB.
- Contribute to pre-silicon verification and post-silicon validation.
🎯 Requirements
- Bachelor's degree in electrical, computer engineering or computer science.
- 10+ years in design verification and test bench development.
- Advanced degree in electrical or computer engineering.
- Experience with UVM/OVM/VMM verification methods.
- Strong object-oriented programming knowledge.
- Strong problem-solving and coding skills.
- Experience in constrained random verification.
- Developing test plans, coverage models, and result analysis.
- Experience with Python for automation.
- RTL design, chip bring-up, and post-silicon validation.
- ITAR: U.S. citizen/national or eligible for export authorizations.
- Active clearance may be required for sensitive missions.
- Willingness to travel for off-site testing.
🎁 Benefits
- Medical, vision, and dental coverage.
- 401(k) retirement plan.
- Disability and life insurance.
- Paid parental leave and vacation.
- 10+ paid holidays per year.
- Employee stock purchase plan.
Meet JobCopilot: Your Personal AI Job Hunter
Automatically Apply to Engineering Jobs. Just set your
preferences and Job Copilot will do the rest — finding, filtering, and applying while you focus on what matters.
Help us maintain the quality of jobs posted on Empllo!
Is this position not a remote job?
Let us know!