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python matlab dsp systemverilog uvm📋 Description
- Responsible for digital ASIC verification at block and system level
- Lead and execute verification test plan, develop test harnesses and sequences
- Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for testing DSP blocks
- Test plan execution, running regressions, code and functional coverage closure
- Automate test case generation using Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up and post-silicon validation
🎯 Requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 8+ years of experience with design verification and test bench development
🎁 Benefits
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Stock options and long-term incentives
- Paid vacation and holidays
- Paid parental leave
- Employee discounts and perks
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