Principal ASIC Design Engineer (Starshield)

📋 Description

• Design digital ASICs and/or FPGAs for Starshield projects.
• Evaluate architectural trade-offs with features and system limits.
• Define micro-architecture; implement RTL in Verilog/SystemVerilog; integrate top-level.
• Work closely with verification team to ensure all aspects are covered and verified.
• Provide timing constraints for IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation; assist in automated test lab equipment.

🎯 Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 10+ years of RTL implementation and/or FPGA/ASIC development.
• Experience solving clock-domain crossings and power optimization.
• Experience developing complex ASICs.
• Experience with multicore CPU subsystem design.
• Experience with standard bus protocols (AXI, AHB) and embedded processors.

🎁 Benefits

• Stock options and long-term incentives.
• Medical, vision, and dental coverage.
• 401(k) retirement plan.
• Disability and life insurance.
• Paid parental leave.
• Paid vacation and holidays; paid sick leave per policy.