Related skills
python fpga asic verilog systemverilog📋 Description
- Design digital ASICs and/or FPGAs for Starshield projects.
- Evaluate architectural trade-offs; derive specs and partition HW/SW with modem/DSP/RFIC.
- Define micro-architecture; implement RTL in Verilog/SystemVerilog; deliver verified design.
- Work with verification team to ensure complete coverage and verification.
- Provide timing constraints for IPs; support synthesis, timing closure, and formality.
- Participate in silicon bring-up and validation; help develop automated test lab equipment.
🎯 Requirements
- Bachelor’s degree in electrical engineering, computer engineering, or computer science.
- 8+ years of RTL implementation and/or FPGA/ASIC development.
- Experience with clock domain crossings and power optimization.
- Experience with standard bus protocols (AXI, AHB) and embedded processors.
- Experience with EDA tools (HDL simulators: VCS/Questa/IES; Spyglass; Xilinx Vivado/Quartus).
- Scripting skills (Python, TCL) and ability to adapt to changing needs.
🎁 Benefits
- Long-term incentives: stock options and/or cash awards; Employee Stock Purchase Plan.
- Medical, vision, and dental coverage; 401(k) retirement plan.
- Disability and life insurance; paid parental leave.
- Discretionary bonuses and stock purchase plan details.
- 3 weeks paid vacation and 10+ paid holidays per year.
- Various discounts and perks.
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