Principal ASIC Design Engineer (Starshield)

📋 Description

• Design digital ASICs/FPGA for Starshield projects.
• Evaluate architectural trade-offs; derive specs with modem/DSP/RFIC teams.
• Define micro-architecture; RTL in Verilog/SystemVerilog; deliver verified design.
• Work with verification team to ensure all aspects are covered.
• Provide timing constraints for IPs; support synthesis, timing closure, formality checks.
• Participate in silicon bring-up and lab equipment development.

🎯 Requirements

• 8+ years RTL implementation and/or FPGA/ASIC development.
• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• Experience solving clock domain crossings and power optimization.
• Experience with multicore CPU subsystem design.
• Experience with standard bus protocols (AXI, AHB, etc.).
• Scripting skills (Python, TCL).

🎁 Benefits

• Long-term incentives, stock options and RSUs.
• Employee stock purchase plan.
• Medical, vision and dental coverage.
• 401(k) retirement plan.
• Paid vacation and holidays.
• Paid sick leave.