Related skills
cmos rtl2gdsii finfetπ Description
- Perform partition synthesis and physical implementation steps (synthesis, floorplanning, P/G grid)
- Develop/improve physical design methodologies and automation scripts
- Collaborate with ASIC design to drive feasibility, timing targets, and RTL/design tradeoffs
- Resolve timing, congestion, and flow issues; drive solutions
- Run, debug, and fix signoff closure in STA, noise, and physical verification
π― Requirements
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development
- Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Understanding of CMOS digital design principles, basic standard cells and their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
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