Related skills
python physical design place and route eda tools staπ Description
- Perform partition synthesis and physical implementation tasks (synthesis, floorplanning, P&R, timing)
- Develop/improve physical design methodologies and automation scripts
- Collaborate with ASIC design team on timing, power, area targets and RTL/design tradeoffs
- Resolve design/timing/congestion issues and drive execution
- Run and fix signoff issues in STA, noise, LVS, electromigration and voltage drop
π― Requirements
- Bachelorβs degree in electrical engineering, computer engineering or computer science
- 3+ years RTL2GDSII physical design and/or flow development experience
- Experience with industry-standard EDA tools
- Knowledge of deep sub-micron FinFET/CMOS physics
- Understanding of CMOS digital design principles and standard cells
- Scripting: Python, TCL, Bash, Perl
- ITAR: US citizen/national or eligible to obtain export authorizations
- Ability to work extended hours and weekends as needed
π Benefits
- Equal Opportunity Employer; accommodations available for applicants with disabilities
- Competitive benefits package
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