New Graduate Engineer, ASIC Design (Starshield)

📋 Description

• Design digital ASICs and/or FPGAs for Starshield projects.
• Evaluate trade-offs; derive specs; partition functions with modem/DSP and RFIC teams.
• Define micro-architecture, RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

🎯 Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• Graduating 2026 or 2027 with a bachelor’s, master’s, or PhD.
• 1+ years of RTL implementation and/or FPGA/ASIC development.
• Proficiency in Verilog/SystemVerilog RTL design.
• Experience with standard bus protocols (AXI, AHB, etc.) and embedded processors.
• Scripting (Python, TCL) and simulators (VCS/Questa/IES).

🎁 Benefits

• Stock incentives and potential long-term bonuses.
• Comprehensive medical, vision, and dental coverage.
• 401(k) retirement plan.
• Disability and life insurance; paid parental leave.
• Paid vacation and holidays; paid sick leave.
• Various discounts and other perks.