Lead ASIC Design Verification Engineer (Starshield Satellite Engineering)
Related skills
python dsp systemverilog uvm rtl📋 Description
- Lead a team for digital ASIC verification at block and system level.
- Lead and execute verification test plans, milestones, and test harnesses.
- Develop SystemVerilog testbenches (UVM and non-UVM) for DSP blocks.
- Oversee test plan execution, running regressions, and coverage closure.
- Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
- Collaborate with engineering leaders to push Starshield satellite performance.
🎯 Requirements
- Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or related field.
- 4+ years of experience with design verification and test bench development.
- Advanced degree in electrical engineering or computer engineering.
- Experience with verification methodologies such as UVM/OVM/VMM.
- Strong object-oriented programming knowledge.
- Experience with scripting languages, e.g. Python for automation.
🎁 Benefits
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks paid vacation and 10+ paid holidays per year
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