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rust python verilog llvm systemverilog📋 Description
- Build and improve tooling: compilation, IR transforms, RTL gen, sim, debug.
- Extend hardware compiler stacks and connect to real design workflows.
- Improve developer experience: reproducible builds, clear errors, CI.
- Collaborate with designers and verification to turn pain points into durable tools.
- Dive into RTL when needed: read Verilog/SystemVerilog to debug.
🎯 Requirements
- Demonstrated ability to build and maintain software projects.
- Strong CS fundamentals: data structures, algorithms, debugging.
- Proficiency in Rust, C++, or Python and willingness to learn others.
- Familiarity with digital design concepts and RTL (Verilog/SystemVerilog).
- Familiarity with compiler or IR based ideas (representations, passes, lowering).
- Comfort operating in ambiguity and iterating quickly with users of your tools.
🎁 Benefits
- Hybrid work arrangement.
- Equity compensation included.
- Work with OpenAI hardware and AI workloads.
- Collaborative, cross disciplinary team.
- Learning and growth opportunities in hardware tooling.
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