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python fpga asic vhdl verilogπ Description
- Design and deploy ML engines on custom hardware for ultra-low latency.
- HW/SW co-design with traders and researchers to implement ML models.
- Shape a greenfield initiative with freedom to explore novel approaches.
- Research NN quantization, compression, and tools bridging ML to RTL.
- See production results quickly via rapid iteration and collaboration.
π― Requirements
- FPGA or ASIC experience with VHDL, Verilog, or SystemVerilog.
- Digital design: pipelining, timing, clock domain crossing.
- FPGA toolchains: Vivado, Quartus, Synplify.
- ML basics: neural nets, inference optimization, quantization.
- Inference for temporal models (RNNs, Transformers) on latency-sensitive hardware.
- Python or C++ for tooling, testing, simulation.
π Benefits
- Discretionary bonus and comprehensive benefits.
- Paid leave and health insurance.
- Collaborative, high-performance culture with global exposure.
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