Related skills
python fpga asic systemverilog rtl📋 Description
- Participate in design architecture discussions and trade-off analysis.
- Write and verify RTL code for high-performance hardware components.
- Support hardware bring-up and provide technical assistance during customer engagements.
🎯 Requirements
- Proficient in SystemVerilog for digital design.
- Familiar with verification tools such as Questa, Incisive, or VCS.
- Experience with scripting (Python, Perl, Tcl) for process automation.
- Solid understanding of ASIC or FPGA logic design.
- Strong self-management, communication, and organizational skills.
- 5+ years of logic design experience and a BSEE degree.
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