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fpga vhdl verilog systemverilog rtl📋 Description
- Lead and mentor a high-performing FPGA team.
- Ensure tools, training, and support for RTL design.
- Provide coaching and regular 1:1s and performance reviews.
- Monitor day-to-day execution across multiple projects.
- Own FPGA lifecycle: architecture to deployment.
- Define scope and milestones with program/product leads.
🎯 Requirements
- Bachelor's degree in Electrical or Computer Engineering
- 5+ years FPGA/RTL design and development
- 3+ years leading or managing engineering teams
- Experience with SystemVerilog/Verilog or VHDL
- Experience with FPGA toolchains: Vivado, Quartus, Libero
- Knowledge of timing closure and high-speed interfaces (SERDES, PCIe, Ethernet)
- Experience with simulation/verification methodologies and tools (UVM, Questa, Verilator)
🎁 Benefits
- Competitive compensation with equity
- Health, dental, and vision insurance for you and dependents
- Unlimited vacation and parental leave
- Relocation packages for approved roles
- $1,500 annual professional development fund
🚚 Relocation support
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